US 12,244,355 B2
Interconnect networks using microLED-based optical links
Robert Kalman, Mountain View, CA (US); Bardia Pezeshki, Mountain View, CA (US); Alexander Tselikov, Mountain View, CA (US); and Cameron Danesh, Mountain View, CA (US)
Assigned to AvicenaTech, Corp., Sunnyvale, CA (US)
Filed by AvicenaTech Corp., Mountain View, CA (US)
Filed on Oct. 26, 2023, as Appl. No. 18/495,689.
Application 18/495,689 is a continuation of application No. 17/229,525, filed on Apr. 13, 2021, granted, now 11,824,590.
Claims priority of provisional application 63/009,199, filed on Apr. 13, 2020.
Prior Publication US 2024/0137132 A1, Apr. 25, 2024
Prior Publication US 2024/0235697 A9, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04B 10/25 (2013.01); G02B 6/43 (2006.01); H01L 33/00 (2010.01); H04B 10/27 (2013.01); H04B 10/40 (2013.01); H04B 10/80 (2013.01); H04J 14/02 (2006.01); H01L 33/10 (2010.01)
CPC H04B 10/803 (2013.01) [G02B 6/43 (2013.01); H01L 33/0045 (2013.01); H04B 10/25 (2013.01); H04B 10/27 (2013.01); H04B 10/40 (2013.01); H04J 14/0217 (2013.01); H01L 33/10 (2013.01)] 14 Claims
OG exemplary drawing
 
1. Optical interconnections for integrated circuit chips, comprising:
a plurality of substrates, each substrate having holes traversing through a body of the substrate from a first side to a second side of the substrate;
a plurality of integrated circuit chips mounted to the plurality of substrates;
a plurality of optoelectronic devices including microLEDs and photodetectors on the plurality of integrated circuit chips, the plurality of optoelectronic devices being within the holes of the plurality of substrates;
a plurality of vertically launched parallel optical links (VLPOLs) optically fitting within the holes of the plurality of substrates and interconnecting at least some of the plurality of optoelectronic devices; and
a plurality of planar launched parallel optical links (PLPOLs) optically interconnecting at least some of the plurality of optoelectronic devices.