US 12,244,326 B2
Encoder and decoder of forward error correction (FEC) codec
Debendra Das Sharma, Saratoga, CA (US); and Swadesh Choudhary, Mountain View, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 19, 2023, as Appl. No. 18/355,332.
Application 18/355,332 is a continuation of application No. 16/900,637, filed on Jun. 12, 2020, granted, now 11,770,138.
Claims priority of provisional application 63/006,979, filed on Apr. 8, 2020.
Prior Publication US 2023/0370095 A1, Nov. 16, 2023
Int. Cl. H03M 13/00 (2006.01); G06F 13/42 (2006.01); H03M 13/15 (2006.01)
CPC H03M 13/6502 (2013.01) [G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01); H03M 13/1575 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A forward error correction (FEC) encoder for generating a check byte for a message, wherein the FEC encoder is to:
generate respective check bytes for second through nth respective sets of the input bytes in respective current clock cycles, wherein to generate the respective check bytes, the FEC encoder is to:
generate, based on a power of an alpha for the respective current clock cycle and a first staged result that is related to one or more previous sets of input bytes of the message for one or more previous clock cycles, a Galois field product for the respective current clock cycle;
generate a consolidated byte related to the respective current clock cycle based on check bytes of the one or more previous sets of input bytes; and
generate, based on the first-Galois field product and the consolidated byte related to the respective current clock cycle, a second staged result;
generate, based on the second staged result of a final set of the n sets of input bytes, the check byte for the message; and
send a signal that includes the check byte for the message over a computer bus.