US 12,244,324 B2
Iterative error correction in memory systems
Marco Sforzin, Boise, ID (US); and Di Hsien Ngu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 19, 2024, as Appl. No. 18/609,417.
Application 18/609,417 is a continuation of application No. 17/843,171, filed on Jun. 17, 2022, granted, now 11,949,428.
Claims priority of provisional application 63/301,028, filed on Jan. 19, 2022.
Prior Publication US 2024/0413840 A1, Dec. 12, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/09 (2006.01); H03K 19/173 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/098 (2013.01) [H03K 19/1737 (2013.01); H03M 13/1171 (2013.01); H03M 13/1174 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for memory error detection and recovery in a decoding system, comprising:
receiving, into a first decoder within the decoding system, a memory transfer block (MTB) (i) comprising data and parity information and having (ii) a vertical portion and a horizontal portion;
performing error detection and correction on the vertical portion of the MTB using binary hamming code logic within the first decoder; and
upon performing error detection and correction in the first decoder, then forwarding MTB to a second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the MTB using a non-binary hamming code logic within the second decoder;
wherein the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the MTB in a serial manner.