US 12,244,322 B2
Alias rejection in analog-to-digital converters (ADCs)
Behnam Sedighi, La Jolla, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 15, 2022, as Appl. No. 17/932,572.
Prior Publication US 2024/0097694 A1, Mar. 21, 2024
Int. Cl. H03M 1/12 (2006.01); H03M 1/46 (2006.01); H03M 1/00 (2006.01)
CPC H03M 1/1265 (2013.01) [H03M 1/466 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01); H03M 1/1225 (2013.01)] 40 Claims
OG exemplary drawing
 
1. An analog-to-digital converter (ADC) circuit comprising:
a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and
a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit, wherein the second circuit portion comprises an analog finite impulse response (FIR) filter operated at the second clock rate.