US 12,244,317 B2
CML to CMOS conversion circuit, receiver circuit and conversion method thereof
Vinod Kumar Jain, Hsinchu (TW); and Mikhail Tamrazyan, Hsinchu (TW)
Assigned to Faraday Technology Corp., Hsinchu (TW)
Filed by Faraday Technology Corp., Hsinchu (TW)
Filed on Jul. 13, 2023, as Appl. No. 18/351,513.
Prior Publication US 2025/0023559 A1, Jan. 16, 2025
Int. Cl. H03K 5/24 (2006.01); H03F 1/32 (2006.01); H03F 3/45 (2006.01)
CPC H03K 5/2481 (2013.01) [H03F 1/3211 (2013.01); H03F 3/45183 (2013.01); H03F 3/45273 (2013.01); H03F 2203/45116 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A conversion circuit, comprising:
a replica feedback loop circuit, comprising a first inverter having a switching threshold voltage, configured to generate a bias voltage based on the switching threshold voltage of the first inverter, wherein an input terminal of the first inverter is electrically connected to an output terminal of the first inverter; and
a current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter, coupled to the replica feedback loop circuit, configured to convert a CML signal to a CMOS signal based on the bias voltage, wherein the CML to CMOS converter comprises a second inverter having a switching threshold voltage that is same as the switching threshold voltage of the first inverter of replica feedback loop circuit,
wherein the bias voltage is configured to set a common-mode (CM) voltage that is input to the second inverter of the CML to CMOS converter to be same as the switching threshold voltage of the second inverter.