US 12,244,316 B2
Semiconductor device having duty-cycle corrector
Yasuo Satoh, Tsukuba (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Apr. 2, 2024, as Appl. No. 18/624,648.
Application 18/624,648 is a division of application No. 17/845,764, filed on Jun. 21, 2022, granted, now 11,973,506.
Prior Publication US 2024/0250675 A1, Jul. 25, 2024
Int. Cl. H03K 5/156 (2006.01); G11C 11/4076 (2006.01)
CPC H03K 5/1565 (2013.01) [G11C 11/4076 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first clock path including a first duty-cycle adjuster configured to adjust a duty-cycle of a first input clock signal;
a second clock path including a second duty-cycle adjuster configured to adjust a duty-cycle of a second input clock signal having a different phase in 90 degrees from the first input clock signal; and
a control circuit configured to detect longest one of first, second, third, and fourth time periods to generate a control signal, wherein the first time period is defined by a phase difference between a rising edge of the first input clock signal and a rising edge of the second input clock signal, the second time period is defined by a phase difference between the rising edge of the second input clock signal and a falling edge of the first input clock signal, the third time period is defined by a phase difference between the falling edge of the first input clock signal and a falling edge of the second input clock signal, and the fourth time period is defined by a phase difference between the falling edge of the second input clock signal and the rising edge of the first input clock signal.