US 12,244,314 B2
Electronic integrator circuit for driving inductor
Thierry Michel Alain Sicard, Auzeville Tolosane (FR)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Sep. 6, 2022, as Appl. No. 17/903,492.
Claims priority of application No. 21306564 (EP), filed on Nov. 8, 2021.
Prior Publication US 2023/0147110 A1, May 11, 2023
Int. Cl. H03K 4/50 (2006.01); H03K 17/687 (2006.01)
CPC H03K 4/50 (2013.01) [H03K 17/6871 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first transistor comprising a first gate, a first drain and a first source;
a second transistor comprising a second gate, a second drain and a second source, the second gate coupled to a first current source configured to generate a linear current ramp, the second source coupled to the first gate and a second current source configured to generate a constant current through the second transistor determined by a sampled voltage between the first gate and the first source;
a third transistor comprising a third gate, a third drain and a third source, the third gate coupled to the first drain, and the third source coupled to an inductive load, wherein the third transistor is configured to source a load current to the inductive load in response to an integration of the linear current ramp; and
a first capacitor coupled between the third source and the second gate, the first capacitor configured to integrate the linear current ramp.