US 12,244,311 B2
Power loss regulation circuit
Je Syu Liu, New Taipei (TW); Chia-Chen Kuo, Hsinchu (TW); Yangsyu Lin, New Taipei (TW); and Cheng Hung Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 28, 2022, as Appl. No. 17/587,616.
Prior Publication US 2023/0246647 A1, Aug. 3, 2023
Int. Cl. H03K 19/0185 (2006.01); G11C 5/14 (2006.01); H03K 19/20 (2006.01)
CPC H03K 19/20 (2013.01) [G11C 5/14 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A circuit in a first power domain, the circuit comprising:
a first enable-controlled logic gate coupled to a second circuit in a second power domain different from the first power domain, wherein an input port of the first enable-controlled logic gate is coupled to an output port of the second circuit;
a feedback loop coupled to the first enable-controlled logic gate, the feedback loop comprising:
a first inverter; and
a second enable-controlled logic gate coupled to the first inverter; and
a second inverter coupled to the feedback loop, wherein an output of the first inverter is coupled to an input of the second enable-controlled logic gate, wherein an output of the second enable-controlled logic gate is coupled to an input of the first inverter, wherein the first enable-controlled logic gate, the first inverter, the second enable-controlled logic gate, and the second inverter are coupled in series.