US 12,244,309 B2
Method of operating a storage device
Elias El Haddad, Grenoble (FR); Tanguy Tromelin, Grenoble (FR); Patrick Bougant, Saint Egreve (FR); and Christophe Matheron, Voreppe (FR)
Assigned to STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed on Jan. 3, 2024, as Appl. No. 18/402,958.
Application 18/402,958 is a continuation of application No. 17/556,365, filed on Dec. 20, 2021, granted, now 11,901,894.
Application 17/556,365 is a continuation of application No. 16/951,645, filed on Nov. 18, 2020, granted, now 11,211,932, issued on Dec. 28, 2021.
Claims priority of application No. 2010332 (FR), filed on Oct. 9, 2020.
Prior Publication US 2024/0137025 A1, Apr. 25, 2024
Prior Publication US 2024/0235555 A9, Jul. 11, 2024
Int. Cl. H03K 19/173 (2006.01)
CPC H03K 19/1737 (2013.01) [H03K 19/1735 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first AND logic gate comprising a first input, a second input, and an output;
a second AND logic gate comprising a first input, a second input, and an output;
a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate;
a first selection circuit having first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate;
a first D latch comprising a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate; and
a second D latch comprising a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate.