CPC H03K 17/6872 (2013.01) | 15 Claims |
1. An apparatus having an input terminal and an output terminal, comprising:
a first transistor having a first gate, a first source, and a first drain, wherein the first source is coupled to the input terminal, and the first drain is coupled to the output terminal;
a second transistor having a second gate, a second source, and a second drain, wherein the second gate is coupled to a ground terminal, and the second source is coupled to the first gate;
a third transistor having a third gate, a third source, and a third drain, wherein the third gate is coupled to an enable signal terminal, the third source is coupled to the ground terminal, and the third drain is coupled to the second drain; and
a fourth transistor having a fourth gate, a fourth source, and a fourth drain, wherein the fourth gate is coupled to the second drain, the fourth source is coupled to the second source, and the fourth drain is coupled to the input terminal.
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