US 12,244,280 B2
Signal processing circuit
Hideaki Majima, Tokyo (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Mar. 26, 2024, as Appl. No. 18/616,377.
Application 18/616,377 is a continuation of application No. 17/392,544, filed on Aug. 3, 2021, granted, now 11,973,477.
Claims priority of application No. 2020-159321 (JP), filed on Sep. 24, 2020.
Prior Publication US 2024/0267013 A1, Aug. 8, 2024
Int. Cl. H03F 3/45 (2006.01); H01P 1/36 (2006.01); H03G 3/30 (2006.01); H03K 5/24 (2006.01)
CPC H03F 3/45475 (2013.01) [H01P 1/36 (2013.01); H03G 3/30 (2013.01); H03K 5/24 (2013.01); H03F 2200/375 (2013.01); H03G 2201/103 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A signal processing circuit, comprising:
an isolator including an input side and an output side that are electrically insulated;
a variable gain amplifier circuit that amplifies an output signal of the isolator;
a DC offset adjustment circuit that adjusts a DC offset of the variable gain amplifier circuit;
a gain adjustment circuit that adjusts a gain of the variable gain amplifier circuit;
a first voltage setting circuit provided on the input side of the isolator, the first voltage setting circuit setting, based on a first control signal, a reference voltage on the input side of the isolator to zero during DC offset adjustment and to a constant voltage different from zero during gain adjustment, and outputting the reference voltage on the input side to the input side of the isolator;
a second voltage setting circuit provided on the output side of the isolator, the second voltage setting circuit setting, based on a second control signal, a reference voltage on the output side of the isolator to zero during DC offset adjustment and to a constant voltage different from zero during gain adjustment, and outputting the reference voltage on the output side to the output side of the isolator;
a comparison circuit that compares an output voltage of the variable gain amplifier circuit with an output voltage of the second voltage setting circuit; and
a control circuit that controls the DC offset adjustment circuit and the gain adjustment circuit in response to an output signal of the comparison circuit, wherein
the first voltage setting circuit includes:
a first differential amplifier circuit that includes an inverting input terminal and a non-inverting input terminal to which constant currents are supplied; and
a first switch provided between the inverting input terminal and the non-inverting input terminal of the first differential amplifier circuit;
the second voltage setting circuit includes:
a second differential amplifier circuit that includes an inverting input terminal and a non-inverting input terminal to which constant currents are supplied; and
a second switch provided between the inverting input terminal and the non-inverting input terminal of the second differential amplifier circuit; and
the control circuit outputs the first and second control signals, and controls on/off of the first and second switches to exclusively control the DC offset adjustment circuit and the gain adjustment circuit.