US 12,244,279 B2
Circuit and method to enhance efficiency of semiconductor device
Bei-Shing Lien, Taipei (TW); and Jaw-Juinn Horng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/360,849.
Application 18/360,849 is a division of application No. 17/146,426, filed on Jan. 11, 2021, granted, now 11,791,786.
Prior Publication US 2023/0387873 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 3/45 (2006.01)
CPC H03F 3/45475 (2013.01) [H03F 2200/129 (2013.01); H03F 2203/45512 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a circuit, comprising:
providing the circuit, the circuit comprising:
an operational amplifier, having a first input terminal, a second input terminal, a first output terminal and a second output terminal;
a plurality of sampling switches, having a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch, the first sampling switch directly coupled to the first input terminal and the first output terminal, the second sampling switch directly coupled to the second input terminal and the second output terminal, the third sampling switch directly coupled to a first node and a first output end, and the fourth sampling switch directly coupled to a second node and a second output end;
a plurality of holding switches, having a first holding switch and a second holding switch, the first holding switch coupled to the first node and the first output terminal, the second holding switch coupled to the second node and the second output terminal; and
a plurality of combined switches, having a first combined switch and a second combined switch, the first combined switch coupled to the first input terminal, the second combined switch coupled to the second input terminal;
during a first phase, causing the plurality of sampling switches to be closed, the plurality of the holding switches to be open, and the plurality of combined switches to be open;
during a second phase, causing the plurality of combined switches to be closed;
during a third phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be open; and
during a fourth phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be closed.