US 12,244,234 B2
Pulse width modulator for a stacked half bridge
Brent McDonald, Murphy, TX (US); and Pradeep Shenoy, Richardson, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 30, 2022, as Appl. No. 17/957,897.
Claims priority of provisional application 63/327,505, filed on Apr. 5, 2022.
Prior Publication US 2023/0318465 A1, Oct. 5, 2023
Int. Cl. H02M 3/335 (2006.01); H02M 1/088 (2006.01)
CPC H02M 3/33571 (2021.05) [H02M 1/088 (2013.01); H02M 3/33507 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a memory; and
a controller coupled to the memory, wherein the controller includes:
a first control output configured to provide a first control signal to a first transistor of a first half bridge power state,
a second control output configured to provide a second control signal to a second transistor coupled to the first transistor,
a third control output configured to provide a third control signal to a third transistor of a second half bridge power stage, and
a fourth control output configured to provide a fourth control signal to a fourth transistor coupled to the first transistor;
wherein the controller is configured to assert the first through fourth control signals to implement a state sequence;
wherein the state sequence includes:
a first state in which the first and fourth transistors are ON and the second and third transistors are OFF,
a second state in which the first and third transistors are ON and the second and fourth transistors are OFF,
a third state in which the second and fourth transistors are ON and the first and third transistors are OFF, and
a fourth state in which the second and third transistors are ON and the first and fourth transistors are OFF; and
wherein during each switching cycle, the controller is configured to implement the first and fourth states with one of the second or third states implemented between instances of the first and fourth states, with every n switching cycles alternating which of the second or third states is implemented between instances of the first and fourth states, where n is an integer.