US 12,244,137 B2
ESD protection for multi-die integrated circuits (ICs) including integrated passive devices
Christian Cornelius Russ, Diedorf (DE); and Kai Esmark, Neuried (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on May 13, 2022, as Appl. No. 17/743,637.
Prior Publication US 2023/0369849 A1, Nov. 16, 2023
Int. Cl. H02H 9/04 (2006.01); H01L 25/065 (2023.01); H01L 27/02 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01)
CPC H02H 9/046 (2013.01) [H01L 25/0655 (2013.01); H01L 27/0255 (2013.01); H01L 27/0266 (2013.01); H01L 27/0288 (2013.01); H01L 27/0292 (2013.01); H01L 23/538 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 25/18 (2013.01); H01L 27/0296 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48175 (2013.01); H01L 2224/49175 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-die semiconductor integrated circuit (IC), comprising:
a first semiconductor die including a first set of pads and a second set of pads, the first set of pads being coupled to respective external pins of an IC package; and
a second semiconductor die including a third set of pads coupled to respective ones of the second set of pads,
wherein the first semiconductor die includes passive electrostatic discharge (ESD) protection circuitry configured to provide passive ESD protection for the first semiconductor die, the passive ESD circuitry comprising only passive ESD protection components, and
wherein the second semiconductor die includes active ESD protection circuitry configured to provide active ESD protection for the first semiconductor die in response to ESD events occurring via the external pins of the IC package to which the first set of pads are coupled.