| CPC H01L 33/62 (2013.01) [H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/156 (2013.01); H01L 29/78696 (2013.01)] | 16 Claims |
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1. A display substrate, comprising:
a plurality of pixel islands, arranged in an array in a first direction and a second direction;
a first opening, located between two pixel islands adjacent in the second direction;
a second opening, located between two pixel islands adjacent in the first direction; and
a first passage region, at least partially located between the first opening and the second opening,
wherein the display substrate is bendable in regions where the first opening and the second opening are located, each of the plurality of pixel islands comprises at least one pixel, the pixel comprises a plurality of first driving lines extending in the first direction, the first passage region is provided with a plurality of first connection lines,
each of the plurality of pixel islands further comprises a plurality of transfer lines extending in the second direction, the plurality of transfer lines are arranged in different layers from the plurality of first driving lines, the plurality of transfer lines and the plurality of first driving lines cross each other to form a plurality of overlapping regions, the plurality of transfer lines are electrically connected with the plurality of first driving lines through via holes located in part of the plurality of overlapping regions,
the transfer lines in two adjacent ones of the plurality of pixel islands in the first direction are respectively connected with the plurality of first connection lines in the first passage region,
the pixel comprises a plurality of sub-pixels, and each of the plurality of sub-pixels comprises a pixel driving circuit and an anode electrically connected with the pixel driving circuit,
wherein the display substrate further comprises:
a base substrate;
a semiconductor layer, located on the base substrate;
a gate insulating layer, located at a side of the semiconductor layer away from the base substrate;
a first gate layer, located at a side of the gate insulating layer away from the semiconductor layer;
an interlayer insulating layer, located at a side of the first gate layer away from the gate insulating layer;
a second gate layer, located at a side of the interlayer insulating layer away from the first gate layer;
a passivation layer, located at a side of the second gate layer away from the interlayer insulating layer; and
a first conductive layer, located at a side of the passivation layer away from the second gate layer,
wherein the plurality of first driving lines are located in at least one of the first gate layer and the second gate layer, and the plurality of transfer lines are located in the first conductive layer,
wherein the pixel driving circuit comprises:
a first semiconductor unit, a second semiconductor unit, a third semiconductor unit, a fourth semiconductor unit, a fifth semiconductor unit, a sixth semiconductor unit and a seventh semiconductor unit located in the semiconductor layer;
a first electrode block, located in the first gate layer; and
a second electrode block, located in the second gate layer,
wherein the first semiconductor unit comprises a first channel region and a first source region and a first drain region on two sides of the first channel region, the second semiconductor unit comprises a second channel region and a second source region and a second drain region on two sides of the second channel region, the third semiconductor unit comprises a third channel region and a third source region and a third drain region on two sides of the third channel region, the fourth semiconductor unit comprises a fourth channel region and a fourth source region and a fourth drain region on two sides of the fourth channel region, the fifth semiconductor unit comprises a fifth channel region and a fifth source region and a fifth drain region on two sides of the fifth channel region, the sixth semiconductor unit comprises a sixth channel region and a sixth source region and a sixth drain region on two sides of the sixth channel region, the seventh semiconductor unit comprises a seventh channel region and a seventh source region and a seventh drain region on two sides of the seventh channel region,
the third source region, the first drain region and the fifth source region are connected to a first node, the sixth drain region is connected to the third drain region, the first source region, the second drain region and the fourth drain region are connected to a second node, the fifth drain region is connected to the seventh drain region,
an orthographic projection of the second electrode block on the base substrate at least partially overlaps with an orthographic projection of the first electrode block on the base substrate to form a storage capacitor.
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