US 12,243,943 B2
Semiconductor device
Takahiro Sato, Tochigi (JP); Yasutaka Nakazawa, Tochigi (JP); Takayuki Cho, Tochigi (JP); Shunsuke Koshioka, Tochigi (JP); Hajime Tokunaga, Yokohama (JP); and Masami Jintyou, Shimotsuga (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jun. 8, 2023, as Appl. No. 18/207,176.
Application 18/207,176 is a continuation of application No. 17/063,748, filed on Oct. 6, 2020, granted, now 11,710,794.
Application 17/063,748 is a continuation of application No. 16/515,283, filed on Jul. 18, 2019, granted, now 10,886,413, issued on Jan. 5, 2021.
Application 16/515,283 is a continuation of application No. 15/785,562, filed on Oct. 17, 2017, granted, now 10,361,318, issued on Jul. 23, 2019.
Application 15/785,562 is a continuation of application No. 15/187,106, filed on Jun. 20, 2016, granted, now 9,812,583, issued on Nov. 7, 2017.
Application 15/187,106 is a continuation of application No. 14/878,399, filed on Oct. 8, 2015, granted, now 9,449,819, issued on Sep. 20, 2016.
Application 14/878,399 is a continuation of application No. 14/733,489, filed on Jun. 8, 2015, granted, now 9,219,165, issued on Dec. 22, 2015.
Application 14/733,489 is a continuation of application No. 14/073,993, filed on Nov. 7, 2013, granted, now 9,087,726, issued on Jul. 21, 2015.
Claims priority of application No. 2012-251794 (JP), filed on Nov. 16, 2012.
Prior Publication US 2023/0317857 A1, Oct. 5, 2023
Int. Cl. H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/465 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/24 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10K 59/123 (2023.01)
CPC H01L 29/7869 (2013.01) [G02F 1/136277 (2013.01); G02F 1/1368 (2013.01); H01L 21/02365 (2013.01); H01L 21/02403 (2013.01); H01L 21/02422 (2013.01); H01L 21/02551 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 21/30604 (2013.01); H01L 21/465 (2013.01); H01L 27/1225 (2013.01); H01L 27/1259 (2013.01); H01L 29/045 (2013.01); H01L 29/0657 (2013.01); H01L 29/1033 (2013.01); H01L 29/24 (2013.01); H01L 29/42356 (2013.01); H01L 29/66742 (2013.01); H01L 29/66969 (2013.01); H01L 29/786 (2013.01); H01L 29/78603 (2013.01); H01L 29/78693 (2013.01); H01L 29/78696 (2013.01); H10K 59/123 (2023.02)] 3 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor including silicon in a channel formation region;
a second transistor over the first transistor, the second transistor including a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, and a second gate electrode over the second insulating film;
a third insulating film and a fourth insulating film over the second transistor; and
a first wiring over the fourth insulating film, the first wiring being electrically connected to a gate electrode of the first transistor and to the oxide semiconductor film via a first opening in the first insulating film, a second opening in the second insulating film, a third opening in the third insulating film, and a fourth opening in the fourth insulating film,
wherein, in a cross-sectional view, the gate electrode of the first transistor and the oxide semiconductor film do not overlap with each other,
wherein the oxide semiconductor film comprises a channel formation region of the second transistor,
wherein, in the cross-sectional view, the first wiring overlaps with the channel formation region of the first transistor, and
wherein, in the cross-sectional view, the first wiring does not overlap with the channel formation region of the second transistor.