| CPC H01L 29/7851 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/02252 (2013.01); H01L 21/02301 (2013.01); H01L 21/823431 (2013.01); H01L 29/0673 (2013.01); H01L 29/157 (2013.01); H01L 29/1604 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01); H01L 29/66545 (2013.01); H01L 2029/7858 (2013.01)] | 13 Claims |

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1. A method of forming a semiconductor device, comprising:
selectively etching a superlattice structure comprising a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs to remove each of the second layers to form a plurality of voids in the superlattice structure, the plurality of first layers extending between a source region and a drain region, and each of the plurality of first layers separated by a silicon oxide (SiOx) inner spacer;
pre-cleaning the plurality of first layers and silicon oxide (SiOx) inner spacer to remove native oxide and/or residues; and
conformally forming an oxide layer on the plurality of first layers and converting the silicon oxide (SiOx) inner spacer to a low-k dielectric inner spacer by radical plasma oxidation (RPO) of the plurality of first layers and the silicon oxide (SiOx) inner spacer, the radical plasma oxidation occurring at a temperature in a range of from about 700° C. to about 900° C. in an atmosphere of hydrogen (H2) gas and oxygen (O2) gas at ambient pressure,
wherein the method is performed in a processing chamber without breaking vacuum.
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