US 12,243,934 B2
Channel structures including doped 2D materials for semiconductor devices
Ching-Hua Lee, Hsinchu (TW); Miao-Syuan Fan, Hsinchu (TW); Ta-Hsiang Kung, New Taipei (TW); and Jung-Wei Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 21, 2023, as Appl. No. 18/452,581.
Application 18/452,581 is a division of application No. 17/400,076, filed on Aug. 11, 2021, granted, now 12,100,755.
Claims priority of provisional application 63/173,297, filed on Apr. 9, 2021.
Prior Publication US 2023/0402534 A1, Dec. 14, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/24 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/76 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7606 (2013.01) [H01L 21/02568 (2013.01); H01L 21/0259 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/1606 (2013.01); H01L 29/24 (2013.01); H01L 29/42392 (2013.01); H01L 29/66969 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a pristine channel layer on the substrate;
forming a two-dimensional (2D) material layer on the pristine channel layer;
performing an ion implantation process onto the 2D material layer to produce a doped 2D material layer;
performing a thermal treatment process to bond the doped 2D material layer to the pristine channel layer;
performing an etching process to form a channel structure; and
forming an interface layer over the channel structure.