US 12,243,932 B2
Negative-capacitance and ferroelectric field-effect transistor (NCFET and FE-FET) devices
Te-Yang Lai, Hsinchu (TW); Chun-Yen Peng, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,377.
Application 17/648,690 is a division of application No. 16/825,874, filed on Mar. 20, 2020, granted, now 11,264,489, issued on Mar. 1, 2022.
Application 18/358,377 is a continuation of application No. 17/648,690, filed on Jan. 24, 2022, granted, now 11,777,017.
Prior Publication US 2023/0369472 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6684 (2013.01) [H01L 21/0228 (2013.01); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/78391 (2014.09)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a ferroelectric dielectric layer over a substrate, forming the ferroelectric dielectric layer comprising:
forming an alternating sequence of dielectric layers, forming the alternating sequence of dielectric layers comprising:
depositing a first dielectric layer over the substrate, wherein at least a part of the first dielectric layer is amorphous; and
forming a plurality of pairs of dielectric layers over the first dielectric layer, forming each pair of layers comprising:
depositing a dopant-source layer comprising dopants; and
depositing a second high-k dielectric layer over the dopant-source layer, wherein at least a part of the second high-k dielectric layer is amorphous; and
after forming the alternating sequence of dielectric layers, performing a first anneal to transform the alternating sequence of dielectric layers to the ferroelectric dielectric layer, wherein an upper surface of an uppermost layer of the second high-k dielectric layer is exposed during the first anneal.