US 12,243,931 B2
Source/drain epitaxial layers for transistors
Wei-Min Liu, Hsinchu (TW); Yee-Chia Yeo, Hsinchu (TW); and Li-Li Su, ChuBei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on May 2, 2023, as Appl. No. 18/311,071.
Application 18/311,071 is a division of application No. 17/072,418, filed on Oct. 16, 2020, granted, now 11,677,013.
Claims priority of provisional application 63/002,293, filed on Mar. 30, 2020.
Prior Publication US 2023/0299180 A1, Sep. 21, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6681 (2013.01) [H01L 29/045 (2013.01); H01L 29/0847 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a fin structure on the substrate comprising a first portion and a second portion taller than the first portion;
an isolation layer on the substrate covering bottom sidewalls of the second portion of the fin structure and sidewalls of the first portion of the fin structure; and
a source/drain (S/D) epitaxial structure on the first portion of the fin structure separated from adjacent S/D epitaxial structures and substantially covering an end portion of the second portion of the fin structure, wherein a distance between a top corner of the end portion and a facet of the S/D epitaxial structure proximal to the top corner is greater than about 2 nm.