US 12,243,930 B2
Semiconductor device with fin end spacer dummy gate and method of manufacturing the same
Kai-Tai Chang, Kaohsiung (TW); Tung-Ying Lee, Hsinchu (TW); Wei-Sheng Yun, Taipei (TW); Tzu-Chung Wang, Hsinchu (TW); Chia-Cheng Ho, Hsinchu (TW); Ming-Shiang Lin, Hsinchu (TW); and Tzu-Chiang Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/875,144.
Application 17/875,144 is a division of application No. 16/562,416, filed on Sep. 5, 2019, granted, now 11,444,174.
Application 16/562,416 is a continuation in part of application No. 16/104,692, filed on Aug. 17, 2018, granted, now 10,797,174, issued on Oct. 6, 2020.
Prior Publication US 2022/0367678 A1, Nov. 17, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01); H01L 21/3105 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/66636 (2013.01); H01L 21/26513 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/31053 (2013.01); H01L 29/1083 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a fin extending in a first direction and having a first edge, a second edge and a middle portion between the first edge and the second edge along the first direction;
a fin liner layer disposed on side face of the fin;
an isolation insulating layer disposed around a bottom portion of the fin;
a gate electrode disposed over the middle portion of the fin;
a spacer dummy gate electrode disposed over the first edge of the fin, the spacer dummy gate electrode including first and second gate sidewall spacers;
a source/drain epitaxial layer disposed between the gate electrode and the spacer dummy gate electrode; and
an oxide layer disposed in direct contact over a portion of an upper surface of the isolation insulating layer and disposed in direct contact with a portion of at least the first gate sidewall spacer when viewed in cross-section,
the oxide layer is disposed in direct contact over portions of an upper surface and side surface of the fin liner layer when viewed in cross-section, and
wherein the spacer dummy gate electrode is entirely formed of a dielectric material.