US 12,243,929 B2
Forming a dummy gate structure
Yan-Ting Shen, Hsinchu (TW); Yu-Li Lin, Kaohsiung (TW); Jui Fu Hsieh, Zhubei (TW); and Chih-Teng Liao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 28, 2022, as Appl. No. 17/661,130.
Prior Publication US 2023/0352559 A1, Nov. 2, 2023
Int. Cl. H01L 29/66 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a polysilicon layer over a plurality of fin structures of a semiconductor device and over one or more shallow trench isolation (STI) regions between the plurality of fin structures;
performing, using a plasma-based etch tool, a dual radio frequency (RF) source etch technique in which a high-frequency RF source and a low-frequency RF source are used to selectively etch a top portion and a bottom portion of the polysilicon layer to form one or more dummy gate structures;
removing, the one or more dummy gate structures from the semiconductor device after one or more subsequent processing operations that are performed after performing the dual RF source etch technique; and
forming, after removal of the one or more dummy gate structures, one or more metal gate structures in place of the one or more dummy gate structures.