US 12,243,925 B2
Transistor gates and method of forming
Hsin-Yi Lee, Hsinchu (TW); Cheng-Lung Hung, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2022, as Appl. No. 17/869,430.
Application 17/869,430 is a division of application No. 16/942,310, filed on Jul. 29, 2020, granted, now 11,404,554.
Claims priority of provisional application 63/025,349, filed on May 15, 2020.
Prior Publication US 2022/0352336 A1, Nov. 3, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/28088 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/1037 (2013.01); H01L 29/4966 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure is disposed over the second nanostructure;
depositing a p-type work function metal over the gate dielectric, wherein after depositing the p-type work function metal, an opening remains between a first portion of the p-type work function metal and a second portion of the p-type work function metal, the first portion of the p-type work function metal and the second portion of the p-type work function metal being between the first nanostructure and the second nanostructure; and
depositing a barrier material over the p-type work function metal using an atomic layer deposition (ALD) process, wherein the barrier material fills the opening between the first portion of the p-type work function metal and the second portion of the p-type work function metal.