US 12,243,922 B2
Method for auto-aligned manufacturing of a VDMOS transistor, and auto-aligned VDMOS transistor
Vincenzo Enea, Syracuse (IT)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed on May 24, 2023, as Appl. No. 18/323,317.
Application 16/684,066 is a division of application No. 15/986,181, filed on May 22, 2018, granted, now 10,510,849, issued on Dec. 17, 2019.
Application 18/323,317 is a continuation of application No. 17/322,514, filed on May 17, 2021, granted, now 11,705,493.
Application 17/322,514 is a continuation of application No. 16/990,606, filed on Aug. 11, 2020, granted, now 11,038,032, issued on Jun. 15, 2021.
Application 16/990,606 is a continuation of application No. 16/684,066, filed on Nov. 14, 2019, granted, now 10,770,558, issued on Sep. 8, 2020.
Claims priority of application No. 102017000057056 (IT), filed on May 25, 2017.
Prior Publication US 2024/0030300 A1, Jan. 25, 2024
Int. Cl. H01L 29/417 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01)
CPC H01L 29/41775 (2013.01) [H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/41741 (2013.01); H01L 29/41766 (2013.01); H01L 29/6656 (2013.01); H01L 29/66719 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01); H01L 21/26513 (2013.01); H01L 21/266 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A device, comprising:
a substrate having a first surface that is opposite to a second surface;
a first doped region in the substrate, the first doped region having a first conductivity type;
a second doped region in the first doped region, the second doped region having a second conductivity type that is different from the first conductivity type;
a third doped region extending through the first doped region, the third doped region having the first conductivity type;
a first opening in the third doped region, the first opening being through the second doped region;
a first electrode in the first opening; and
a second electrode in the substrate, the second doped region being between the first electrode and the second electrode.