US 12,243,921 B2
Vertical gallium oxide (GA2O3) power FETs
Zongyang Hu, Ithaca, NY (US); Kazuki Nomoto, Ithaca, NY (US); Grace Huili Xing, Ithaca, NY (US); Debdeep Jena, Ithaca, NY (US); and Wenshen Li, Ithaca, NY (US)
Assigned to Cornell University, Ithaca, NY (US)
Filed by Cornell University, Ithaca, NY (US)
Filed on Jun. 13, 2023, as Appl. No. 18/209,323.
Application 18/209,323 is a division of application No. 17/042,153, granted, now 11,715,774, previously published as PCT/US2019/024634, filed on Mar. 28, 2019.
Claims priority of provisional application 62/649,281, filed on Mar. 28, 2018.
Prior Publication US 2023/0326984 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/417 (2006.01); C30B 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/41741 (2013.01) [C30B 29/16 (2013.01); H01L 29/66969 (2013.01); H01L 29/7827 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A vertical gallium oxide (Ga2O3) device comprising: a
substrate;
an n-type Ga2O3 drift layer disposed on a surface of the substrate;
an n-type semiconducting channel extending from a surface of the n-type Ga2O3 drift layer, the n-type semiconducting channel being one of fin-shaped or nanowire shaped; an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the n-type semiconducting channel; no p-type semiconducting layer being used in the vertical gallium oxide (Ga2O3) device;
a first dielectric layer directly on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel;
a conductive gate layer deposited on at least a portion of the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer;
a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls; and
an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer; and
a resistive terminal component extending from a first lateral surface of the n-type Ga2O3 drift layer to a second lateral surface of the n-type Ga2O3 drift layer and from said surface of the n-type Ga2O3 drift layer and another surface of the n-type Ga2O3 drift layer, said another surface located between said surface of the n-type Ga2O3 drift layer and said surface of the substrate.