US 12,243,920 B2
Method to form selective high-k deposition on 2D materials
Mark I. Gardner, Albany, NY (US); and H. Jim Fulford, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Jan. 12, 2022, as Appl. No. 17/574,533.
Prior Publication US 2023/0223449 A1, Jul. 13, 2023
Int. Cl. H01L 29/40 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/408 (2013.01) [H01L 29/0649 (2013.01); H01L 29/78618 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, comprising:
forming a seed structure on a base layer;
depositing an isolation material over the base layer to laterally surround the seed structure;
polishing the seed structure and the isolation material;
etching a portion of the isolation material to expose sidewalls of the seed structure;
forming source/drain metal structures extending along the sidewalls of the seed structure, respectively;
forming a two-dimensional (2D) semiconductor layer from at least the seed structure, wherein the 2D semiconductor layer is formed on a top surface of the seed structure and a top surface of each of the source/drain metal structures; and
forming a high-k dielectric layer on the 2D semiconductor layer.