US 12,243,919 B2
Method and structure for metal gate boundary isolation
Shahaji B. More, Hsinchu (TW); and Chandrashekhar Prakash Savant, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 18, 2023, as Appl. No. 18/319,999.
Application 18/319,999 is a continuation of application No. 17/233,355, filed on Apr. 16, 2021, granted, now 11,658,216.
Claims priority of provisional application 63/137,569, filed on Jan. 14, 2021.
Prior Publication US 2023/0299153 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01)
CPC H01L 29/401 (2013.01) [H01L 21/28061 (2013.01); H01L 21/28079 (2013.01); H01L 21/823842 (2013.01); H01L 27/0924 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first transistor adjacent a second transistor, wherein the first transistor includes a first gate metal layer directly on a gate dielectric layer, and the second transistor includes a second gate metal layer directly on the gate dielectric layer, wherein the first and the second gate metal layers include different materials; and
a first barrier disposed horizontally between the first gate metal layer and the second gate metal layer, wherein one of the first and the second gate metal layers includes aluminum, and the first barrier has low permeability for aluminum, wherein a bottom surface of the second gate metal layer is directly on a top surface of the first barrier.