US 12,243,913 B2
Self-aligned backside contact integration for transistors
Nikhil Jain, Apple Valley, MN (US); Sagarika Mukesh, Albany, NY (US); Devika Sarkar Grant, Amsterdam, NY (US); Prabudhya Roy Chowdhury, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); and Kisik Choi, Watervliet, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Feb. 23, 2022, as Appl. No. 17/652,113.
Prior Publication US 2023/0268389 A1, Aug. 24, 2023
Int. Cl. H01L 29/786 (2006.01); H01L 23/48 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/0665 (2013.01) [H01L 23/481 (2013.01); H01L 29/0649 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a transistor comprising a plurality of source/drain epitaxies; and
at least one backside power rail under the transistor;
a backside inter-layer dielectric (ILD) located between the plurality of source/drain epitaxies and the at least one power rail;
a first backside contact connecting a first source/drain epitaxy to the at least one backside power rail;
one or more contact placeholders formed under the other source/drain epitaxies; and
a backside power distribution network (BSPDN) connected to the at least one backside power rail opposite the transistor.