US 12,243,912 B2
Source/drain feature for multigate device performance and method of fabricating thereof
Chih-Chuan Yang, Hsinchu (TW); Wen-Chun Keng, Hsinchu County (TW); Chong-De Lien, Hsinchu (TW); Shih-Hao Lin, Hsinchu (TW); Hsin-Wen Su, Hsinchu (TW); and Ping-Wei Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Dec. 15, 2021, as Appl. No. 17/552,111.
Claims priority of provisional application 63/188,526, filed on May 14, 2021.
Prior Publication US 2022/0367620 A1, Nov. 17, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/764 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 21/0259 (2013.01); H01L 21/764 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor layer stack disposed over a mesa structure of a substrate;
a metal gate disposed over the semiconductor layer stack;
an inner spacer disposed on the mesa structure of the substrate;
a first epitaxial source/drain feature and a second epitaxial source/drain feature, wherein the semiconductor layer stack is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature and each of the first epitaxial source/drain feature and the second epitaxial source/drain feature includes a first epitaxial layer interfacing the semiconductor layer stack and a second epitaxial layer spaced apart from the semiconductor layer stack by the first epitaxial layer;
a void disposed between the inner spacer and the first epitaxial source/drain feature; and
a contact isolation layer disposed over the first epitaxial source/drain feature to interface the first epitaxial layer of the first epitaxial source/drain feature.
 
14. A semiconductor structure, comprising:
a mesa arising from a substrate;
a first plurality of channel layers disposed over the mesa;
a second plurality of channel layers disposed over the mesa;
a source/drain feature extending between the first plurality of channel layers and the second plurality of channel layers, wherein the source/drain feature comprises a first epitaxial layer in contact with the first plurality of channel layers and the second plurality of channel layers and a second epitaxial layer spaced apart from the first plurality of channel layers and the second plurality of channel layers by the first epitaxial layer;
a contact isolation layer disposed over the source/drain feature to contact with the first epitaxial layer; and
a void disposed between a bottom surface of the source/drain feature and the mesa,
wherein the void is spaced apart from the mesa by a bottom inner spacer.