US 12,243,910 B2
Silicon carbide semiconductor device with overlapping electric field relaxation regions and method of manufacturing the same
Shinichirou Miyahara, Kariya (JP); Masatoshi Tsujimura, Nagakute (JP); and Yusuke Yamashita, Nagakute (JP)
Assigned to DENSO CORPORATION, Kariya (JP)
Filed by DENSO CORPORATION, Kariya (JP)
Filed on Apr. 12, 2022, as Appl. No. 17/718,792.
Application 17/718,792 is a continuation of application No. PCT/JP2020/038773, filed on Oct. 14, 2020.
Claims priority of application No. 2019-197841 (JP), filed on Oct. 30, 2019.
Prior Publication US 2022/0246719 A1, Aug. 4, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 21/04 (2006.01); H01L 21/76 (2006.01); H01L 21/761 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/063 (2013.01) [H01L 21/046 (2013.01); H01L 21/7602 (2013.01); H01L 21/761 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7813 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A silicon carbide semiconductor device comprising:
a substrate made of silicon carbide having a first conductivity type or a second conductivity type, and having a front surface and a rear surface opposite to each other;
a drift layer disposed on the front surface of the substrate and made of silicon carbide having the first conductivity type with an impurity concentration lower than an impurity concentration of the substrate;
a base region disposed on the drift layer and made of silicon carbide having the second conductivity type;
a source region disposed in an upper layer portion of the base region and made of silicon carbide having the first conductivity type with an impurity concentration higher than the impurity concentration of the drift layer;
a contact region disposed at a position different from the source region in the upper layer portion of the base region, and made of silicon carbide having the second conductivity type with an impurity concentration higher than the impurity concentration of the base region;
a trench gate structure including a plurality of trenches provided from a surface of the source region to a position deeper than the base region and arranged in parallel with one direction as a longitudinal direction, a gate insulating film covering an inner wall of each of the plurality of trenches, and a gate electrode disposed in each of the plurality of trenches via the gate insulating film;
a source electrode electrically connected to the source region and the contact region;
a drain electrode disposed on the rear surface of the substrate; and
an electric field relaxation layer disposed in the drift layer and including a first region and a second region, the first region having the second conductivity type and disposed at a position deeper than the plurality of trenches, the second region having the second conductivity type and disposed between adjacent trenches in the plurality of trenches to be away from a side surface of each of the adjacent trenches, the second region having a longitudinal direction in a same direction as the longitudinal direction of the plurality of trenches and connecting the first region and the base region, wherein
each of the first region and the second region is made of an ion implantation layer,
the electric field relaxation layer further includes a double implantation region in which the first region and the second region overlap with each other, and
the electric field relaxation layer has a peak of a second conductivity type impurity concentration in the double implantation region.