| CPC H01L 28/75 (2013.01) [H01L 27/0733 (2013.01); H01L 28/40 (2013.01); H01L 28/91 (2013.01); H01L 28/92 (2013.01); H01L 29/945 (2013.01)] | 20 Claims |
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1. An integrated chip comprising:
a lower conductive wire over a substrate;
a dielectric structure over the lower conductive wire;
an upper conductive wire spaced over the lower conductive wire;
a first capacitor between sidewalls of the dielectric structure and between the lower conductive wire and the upper conductive wire, the first capacitor including a first electrode and a second electrode;
a second capacitor between the sidewalls of the dielectric structure and between the first capacitor and the upper conductive wire, the second capacitor including the second electrode and a third electrode; and
a third capacitor between the sidewalls of the dielectric structure and between the second capacitor and the upper conductive wire, the third capacitor including the third electrode and a fourth electrode,
wherein first electrode and the third electrode are coupled to the lower conductive wire, and the second electrode and the fourth electrode are coupled to the upper conductive wire such that the first capacitor, the second capacitor, and the third capacitor are coupled in parallel between the lower conductive wire and the upper conductive wire.
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