US 12,243,900 B2
Solid-state imaging apparatus and imaging apparatus including the same
Makoto Ikuma, Hyogo (JP); Hiroyuki Amikawa, Ishikawa (JP); and Yutaka Abe, Osaka (JP)
Assigned to NUVOTON TECHNOLOGY CORPORATION JAPAN, Kyoto (JP)
Filed by Nuvoton Technology Corporation Japan, Kyoto (JP)
Filed on Aug. 2, 2022, as Appl. No. 17/879,428.
Application 17/879,428 is a continuation of application No. PCT/JP2021/003103, filed on Jan. 28, 2021.
Claims priority of application No. 2020-025065 (JP), filed on Feb. 18, 2020.
Prior Publication US 2022/0367557 A1, Nov. 17, 2022
Int. Cl. H01L 27/146 (2006.01); H04N 25/59 (2023.01); H04N 25/65 (2023.01); H04N 25/75 (2023.01); H04N 25/771 (2023.01); H04N 25/778 (2023.01)
CPC H01L 27/14643 (2013.01) [H01L 27/14609 (2013.01); H04N 25/59 (2023.01); H04N 25/65 (2023.01); H04N 25/75 (2023.01); H04N 25/771 (2023.01); H04N 25/778 (2023.01)] 23 Claims
OG exemplary drawing
 
1. A solid-state imaging apparatus comprising:
a pixel circuit; and
a negative feedback circuit, wherein:
the pixel circuit includes:
a photodiode;
a charge storage;
a transfer transistor that transfers a signal charge generated by the photodiode to the charge storage;
an amplification transistor that outputs a pixel signal corresponding to a signal charge in the charge storage;
a first reset transistor that resets the charge storage;
a first storage capacitive element; and
a first transistor that controls a connection between the charge storage and the first storage capacitive element,
the negative feedback circuit negatively feeds back a feedback signal according to a reset output of the amplification transistor to the charge storage via the first reset transistor,
the first transistor is connected between the first reset transistor and the charge storage, in series with the first reset transistor,
the first storage capacitive element is connected to a connection point of the first reset transistor and the first transistor, and
the solid-state imaging apparatus further comprises:
a second transistor inserted in series between the first transistor and the charge storage; and
a second storage capacitive element that is connected to (i) a connection point of the first transistor and the second transistor and (ii) the charge storage via the second transistor.