US 12,243,899 B2
Imaging device and electronic apparatus
Junichiro Fujimagari, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/290,824
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Oct. 18, 2019, PCT No. PCT/JP2019/041068
§ 371(c)(1), (2) Date May 3, 2021,
PCT Pub. No. WO2020/100520, PCT Pub. Date May 22, 2020.
Claims priority of application No. 2018-212463 (JP), filed on Nov. 12, 2018.
Prior Publication US 2021/0375976 A1, Dec. 2, 2021
Int. Cl. H01L 27/14 (2006.01); H01L 27/146 (2006.01); H04N 25/76 (2023.01)
CPC H01L 27/14643 (2013.01) [H01L 27/14621 (2013.01); H01L 27/14623 (2013.01); H01L 27/14625 (2013.01); H01L 27/14636 (2013.01); H01L 27/1464 (2013.01); H04N 25/76 (2023.01)] 10 Claims
OG exemplary drawing
 
1. An imaging device, comprising:
a semiconductor layer that comprises:
a first surface configured to serve as a light incident surface; and
a second surface opposed to the first surface;
a light reception region in the first surface, wherein the light reception region includes a plurality of photoelectric converters configured to perform photoelectric conversion on incident light;
a peripheral region in the first surface, wherein the peripheral region is around the light reception region;
a through via that penetrates between the first surface and the second surface;
a first coupling section on the peripheral region on a side of the first surface, wherein a width of the first coupling section is wider than a width of the through via;
a second coupling section on the peripheral region on the side of the first surface, wherein the second coupling section is configured to couple to an external substrate;
a first semiconductor element that includes a coupling wiring line, wherein the coupling wiring line is configured to electrically couple the first coupling section, the second coupling section, and the through via to one another; and
a second semiconductor element that is mounted on the first semiconductor element via the first coupling section, wherein the second semiconductor element is coupled to the first coupling section via a solder.