US 12,243,884 B2
Semiconductor device and solid-state imaging sensor
Katsuhiko Fukasaku, Kanagawa (JP); Koichi Matsumoto, Kanagawa (JP); and Akito Shimizu, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/282,805
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Oct. 2, 2019, PCT No. PCT/JP2019/038840
§ 371(c)(1), (2) Date Apr. 5, 2021,
PCT Pub. No. WO2020/075583, PCT Pub. Date Apr. 16, 2020.
Claims priority of application No. 2018-193723 (JP), filed on Oct. 12, 2018; and application No. 2019-119168 (JP), filed on Jun. 26, 2019.
Prior Publication US 2021/0391366 A1, Dec. 16, 2021
Int. Cl. H01L 27/146 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/14616 (2013.01) [H01L 29/0692 (2013.01); H01L 29/4236 (2013.01); H01L 29/7827 (2013.01)] 27 Claims
OG exemplary drawing
 
2. A semiconductor device, comprising:
a low-concentration N-type region;
a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, and that have a higher concentration of impurity than the low-concentration N-type region;
a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked;
a first insulating film placed between the gate electrode and the low-concentration N-type region; and
a second insulating film placed between the gate electrode and the first high-concentration N-type region, wherein
the first high-concentration N-type region is connected to a first one of a source electrode and a drain electrode; and
the second high-concentration N-type region is connected to a second one of the source electrode and the drain electrode,
wherein the first high-concentration N-type region includes a facing region that is a region facing the low-concentration N-type region with the gate electrode interposed therebetween,
wherein the semiconductor device further comprises a third insulating film placed between the facing region and the gate electrode, and
wherein a thickness of the third insulating film is thicker than a thickness of the first insulating film and a thickness of the second insulating film.