US 12,243,881 B2
Logic circuit and semiconductor device
Shunpei Yamazaki, Setagaya (JP); Jun Koyama, Sagamihara (JP); Masashi Tsubuku, Atsugi (JP); and Kosei Noda, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Aug. 30, 2023, as Appl. No. 18/239,928.
Application 18/239,928 is a continuation of application No. 17/980,693, filed on Nov. 4, 2022, granted, now 11,756,966.
Application 17/980,693 is a continuation of application No. 17/340,165, filed on Jun. 7, 2021, abandoned.
Application 17/340,165 is a continuation of application No. 16/816,806, filed on Mar. 12, 2020, granted, now 11,056,515, issued on Jul. 6, 2021.
Application 16/816,806 is a continuation of application No. 16/008,437, filed on Jun. 14, 2018, granted, now 10,593,710, issued on Mar. 17, 2020.
Application 16/008,437 is a continuation of application No. 15/469,888, filed on Mar. 27, 2017, granted, now 10,002,891, issued on Jun. 19, 2018.
Application 15/469,888 is a continuation of application No. 15/332,323, filed on Oct. 24, 2016, granted, now 9,947,695, issued on Apr. 17, 2018.
Application 15/332,323 is a continuation of application No. 14/570,553, filed on Dec. 15, 2014, granted, now 9,553,583, issued on Jan. 24, 2017.
Application 14/570,553 is a continuation of application No. 12/902,670, filed on Oct. 12, 2010, granted, now 8,952,726, issued on Feb. 10, 2015.
Claims priority of application No. 2009-238918 (JP), filed on Oct. 16, 2009.
Prior Publication US 2023/0411410 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); G09G 3/20 (2006.01); G09G 3/3233 (2016.01); G09G 3/3291 (2016.01); G09G 3/36 (2006.01); G11C 19/18 (2006.01); G11C 19/28 (2006.01); H01L 29/786 (2006.01); H03K 17/16 (2006.01); H03K 19/003 (2006.01); H03K 19/096 (2006.01)
CPC H01L 27/1255 (2013.01) [G09G 3/20 (2013.01); G09G 3/2092 (2013.01); G09G 3/3291 (2013.01); G09G 3/36 (2013.01); G11C 19/184 (2013.01); G11C 19/28 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 29/7869 (2013.01); H03K 17/161 (2013.01); H03K 19/00315 (2013.01); H03K 19/096 (2013.01); G09G 3/3233 (2013.01); G09G 3/3648 (2013.01); G09G 2300/0439 (2013.01); G09G 2300/08 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a pixel portion having a first transistor and a light-emitting element electrically connected to the first transistor; and
a drive circuit electrically connected to the pixel portion and having a second transistor,
the first transistor comprises:
a first source electrode layer and a first drain electrode layer;
a first oxide semiconductor layer having regions in contact with top surfaces and side surfaces of the first source electrode layer and the first drain electrode layer; and
a first gate electrode layer over the first oxide semiconductor layer with a first gate insulating layer interposed therebetween,
the second transistor comprises:
a second gate electrode layer;
a second source electrode layer and a second drain electrode layer over the second gate electrode layer;
a second oxide semiconductor layer having regions in contact with top surfaces and side surfaces of the second source electrode layer and the second drain electrode layer; and
a third gate electrode layer over the second oxide semiconductor layer with a second gate insulating layer interposed therebetween,
wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise indium, gallium, and zinc.