US 12,243,878 B2
Active matrix substrate and display device
Hikaru Yoshino, Kameyama (JP); Satoshi Horiuchi, Kameyama (JP); and Junichi Morinaga, Kameyama (JP)
Assigned to SHARP DISPLAY TECHNOLOGY CORPORATION, Kameyama (JP)
Filed by Sharp Display Technology Corporation, Kameyama (JP)
Filed on Oct. 11, 2022, as Appl. No. 17/963,287.
Claims priority of application No. 2021-167741 (JP), filed on Oct. 12, 2021; and application No. 2022-123514 (JP), filed on Aug. 2, 2022.
Prior Publication US 2023/0112631 A1, Apr. 13, 2023
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01)
CPC H01L 27/124 (2013.01) [G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H01L 27/1255 (2013.01); G02F 1/133345 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An active matrix substrate comprising:
a substrate in which a notch or an aperture is formed;
a plurality of gate lines formed in a gate line layer on the substrate;
a plurality of source lines formed in a source line layer that is a layer different from the gate line layer, the source lines being arranged to intersect with the gate lines when viewed in a plan view; and
an electrode at least a part of which is formed in an electrode layer that is a layer different from any of the gate line layer and the source line layer,
wherein the gate lines include a plurality of bypass gate lines that are bent or curved to bypass the notch or the aperture,
the substrate includes a bypass region through which the bypass gate lines pass for bypassing, and in which a distance between the bypass gate lines is smaller than a distance between the bypass gate lines in a region other than the bypass region,
the electrode includes at least either of:
a capacitor forming portion that is arranged in the region other than the bypass region and overlaps with at least one of the bypass gate lines when viewed in a plan view; and
an electrode layer portion that is formed in the electrode layer and that composes a bypass gate line interposed portion together with a source line layer portion formed in the source line layer in the bypass region, and
the electrode layer portion overlaps with at least one of the bypass gate lines in the bypass region when viewed in a plan view,
the source line layer portion overlaps with the at least one of the bypass gate lines at a position in which the electrode layer portion overlaps with the at least one of the bypass gate lines when viewed in a plan view, and
the at least one of the bypass gate lines is positioned between the electrode layer portion and the source line layer portion in the position in a normal line direction of the substrate.