US 12,243,875 B2
Forksheet transistors with dielectric or conductive spine
Seung Hoon Sung, Portland, OR (US); Cheng-Ying Huang, Portland, OR (US); Marko Radosavljevic, Portland, OR (US); Christopher M. Neumann, Portland, OR (US); Susmita Ghose, Hillsboro, OR (US); Varun Mishra, Hillsboro, OR (US); Cory Weber, Hillsboro, OR (US); Stephen M. Cea, Hillsboro, OR (US); Tahir Ghani, Portland, OR (US); and Jack T. Kavalieros, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 10, 2024, as Appl. No. 18/409,519.
Application 18/409,519 is a continuation of application No. 17/030,226, filed on Sep. 23, 2020, granted, now 11,923,370.
Prior Publication US 2024/0153956 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); H01L 21/84 (2006.01)
CPC H01L 27/1203 (2013.01) [H01L 21/84 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a dielectric spine;
a first transistor device comprising a first semiconductor channel spaced apart from a first edge of the dielectric spine;
a second transistor device comprising a second semiconductor channel spaced apart from a second edge of the dielectric spine;
an N-type gate structure on the first semiconductor channel, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first semiconductor channel; and
a P-type gate structure on the second semiconductor channel, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second semiconductor channel.