US 12,243,874 B2
Method of forming a static random-access memory (SRAM) cell with fin field effect transistors
Kyungin Choi, Seoul (KR); Jinbum Kim, Seoul (KR); Haejun Yu, Osan-si (KR); and Seung Hun Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 5, 2023, as Appl. No. 18/143,767.
Application 18/143,767 is a continuation of application No. 17/231,502, filed on Apr. 15, 2021, granted, now 11,682,673.
Claims priority of application No. 10-2020-0103300 (KR), filed on Aug. 18, 2020.
Prior Publication US 2023/0275092 A1, Aug. 31, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 29/41791 (2013.01); H01L 29/66553 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
forming active patterns by patterning a substrate;
forming a spacer layer covering top surfaces and both side surfaces of the active patterns;
forming a buffer layer on the spacer layer, which has a dielectric constant higher than a dielectric constant of the spacer layer;
forming a first hard mask pattern on the buffer layer;
etching the first hard mask pattern such that a top surface of the first hard mask pattern is located at a level lower than the top surfaces of the active patterns;
performing a wet etching process to the buffer layer;
forming recesses by etching the active patterns such that the top surfaces of the active patterns are disposed below tipper surfaces of the spacer layer; and
forming source/drain patterns to fill the recesses.