| CPC H01L 27/0255 (2013.01) [H01L 23/5226 (2013.01); H01L 29/417 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 13 Claims |
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1. A semiconductor device comprising:
a substrate in a first level;
a source line in a second level above the first level in a first direction perpendicular to a surface of the substrate;
a plurality of word lines provided in a third level above the second level in the first direction, the plurality of word lines being separated from each other in the first direction;
a first plug penetrating the plurality of word lines in the third level and electrically connected to the source line, a plurality of memory cells being provided between cross sections of the plurality of word lines and the first plug;
first and second diffusion layers provided in the substrate in the first level separately, one of the first and second diffusion layers functioning as an anode layer of an ESD (electrostatic discharge) protection circuit, the other of the first and second diffusion layers functioning as a cathode layer of the ESD protection circuit;
a second plug provided in the second level and the third level at a position that overlaps with the first diffusion layer in the first direction, the second plug being electrically connected with the first diffusion layer;
a third plug provided in the second level and the third level at a position that does not overlap with the first diffusion layer and the second diffusion layer in the first direction, the third plug being electrically connected with the first diffusion layer;
a fourth plug provided in the second level and the third level at a position that overlaps with the second diffusion layer in the first direction, the fourth plug provided between the second plug and the third plug in a second direction intersecting the first direction;
a plurality of interconnects provided in a fourth level between the first level and the second level, the plurality of interconnects electrically connected to the third plug and the first diffusion layer that is electrically connected to the second plug;
a first upper interconnect provided above the third level in the first direction, and electrically connected with the second plug and the third plug; and
a second upper interconnect provided above the third level in the first direction, electrically connected with the fourth plug, and not electrically connected with the first upper interconnect,
wherein the first plug, the second plug, the third plug, and the fourth plug are provided in the third level.
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