US 12,243,856 B2
Fan out packaging pop mechanical attach method
David O'Sullivan, Ottobrunn (DE); Georg Seidemann, Landshut (DE); Richard Patten, Langquaid (DE); and Bernd Waidhas, Pettendorf (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 30, 2023, as Appl. No. 18/217,000.
Application 18/217,000 is a continuation of application No. 15/945,648, filed on Apr. 4, 2018, granted, now 11,735,570.
Prior Publication US 2023/0343766 A1, Oct. 26, 2023
Int. Cl. H01L 25/10 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/96 (2013.01); H01L 25/50 (2013.01); H01L 2224/214 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first die having a top side and a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall, and the first die having a first conductive pad and a second conductive pad on the top side;
a redistribution layer on the bottom side of the first die, the redistribution layer extending laterally beyond the first sidewall and the second sidewall of the first die;
a mold layer on the redistribution layer and laterally adjacent to the first sidewall and the second sidewall of the first die, the mold layer having an uppermost surface;
a first via in the mold layer and laterally spaced apart from the first sidewall of the first die;
a second via in the mold layer and laterally spaced apart from the second sidewall of the first die;
a third conductive pad on the first via, the third conductive pad having an uppermost surface above the uppermost surface of the mold layer;
a fourth conductive pad on the second via, the fourth conductive pad having an uppermost surface above the uppermost surface of the mold layer;
a second die over the first die and over the first via, the second die coupled to the first conductive pad and the third conductive pad;
a third die over the first die and over the second via, the third die coupled to the second conductive pad and the fourth conductive pad; and
a plurality of solder balls beneath and coupled to the redistribution layer, the plurality of solder balls vertically beneath the first die and the mold layer.