US 12,243,855 B2
Package comprising channel interconnects located between solder interconnects
Aniket Patil, San Diego, CA (US); Durodami Lisk, San Diego, CA (US); Hong Bok We, San Diego, CA (US); and Charles David Paynter, Encinitas, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 22, 2021, as Appl. No. 17/532,754.
Prior Publication US 2023/0163113 A1, May 25, 2023
Int. Cl. H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 25/50 (2013.01); H01L 2224/16227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first package comprising:
a first substrate comprising at least one first dielectric layer and a first plurality of interconnects; and
a first integrated device coupled to the first substrate; and
a second package comprising:
a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, wherein the second substrate is coupled to the first substrate through a first plurality of solder interconnects;
a second integrated device coupled to a first surface of the second substrate;
a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects; and
a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located laterally between solder interconnects from the second plurality of solder interconnects.