US 12,243,852 B2
Semiconductor package and manufacturing method thereof
Akihito Sawanobori, Yokkaichi (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jul. 17, 2023, as Appl. No. 18/353,343.
Application 18/353,343 is a division of application No. 17/016,594, filed on Sep. 10, 2020, granted, now 11,749,646.
Claims priority of application No. 2020-017171 (JP), filed on Feb. 4, 2020.
Prior Publication US 2023/0361084 A1, Nov. 9, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/552 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/49822 (2013.01); H01L 23/552 (2013.01); H01L 24/48 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/3025 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor package, comprising:
placing a semiconductor chip on a substrate;
covering the semiconductor chip with a resin layer;
covering a surface and side surfaces of the resin layer with a first metal layer;
depositing a second metal layer including a first metal material that is different from a material of the first metal layer at a temperature of 150 degrees or higher;
depositing a third metal layer including an alloy of the first metal material forming the second metal layer and a second metal material different from the first metal material; and
covering the second or third metal layer with a fourth metal layer, wherein
content of the second metal material included in the third metal layer is 1 to 20 atomic percent,
a grain size in the second metal layer is 0.10 μm or more,
a grain size in the third metal layer is less than 0.10 μm,
a total thickness of the second and third metal layers is in a range of 0.45 μm to 2.5 μm,
a resistance value of the second metal layer is lower than resistance values of the first, third, and fourth metal layers,
the second metal layer is provided on the first metal layer,
the third metal layer is provided on the second metal layer, and
the fourth metal layer is provided on the third metal layer.