| CPC H01L 25/0657 (2013.01) [H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/94 (2013.01); H01L 2224/0613 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48225 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01)] | 20 Claims |

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1. A package, comprising:
a first chip stack including:
a first chip including first bonding structures;
a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures; and
a first electrical contact on the second chip, wherein at least a portion of the first electrical contact does not overlap with the first chip in a plan view;
a second chip stack adhering to the first chip stack and including:
a third chip including third bonding structures;
a fourth chip including fourth bonding structures facing the third bonding structures and bonded to the third bonding structures; and
a second electrical contact on the fourth chip, wherein at least a portion of the second electrical contact does not overlap with the third chip in the plan view, wherein the first chip and the third chip have a same first footprint, and wherein the second chip and the fourth chip have a same second footprint different than the first footprint.
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