US 12,243,842 B2
Semiconductor device with open cavity and method therefor
Michael B. Vincent, Chandler, AZ (US); and Scott M. Hayes, Chandler, AZ (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, INC., Austin, TX (US)
Filed on Dec. 8, 2021, as Appl. No. 17/643,198.
Prior Publication US 2023/0178508 A1, Jun. 8, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01); H01L 23/498 (2006.01); H01R 12/57 (2011.01)
CPC H01L 24/24 (2013.01) [H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/315 (2013.01); H01L 24/82 (2013.01); H01L 25/0655 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 23/49827 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/19 (2013.01); H01L 2224/211 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/2402 (2013.01); H01L 2224/24155 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/82101 (2013.01); H01L 2224/82105 (2013.01); H01L 2224/82951 (2013.01); H01R 12/57 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
placing a semiconductor die and routing structure on a carrier substrate, the routing structure including a non-conductive substrate and a plurality of conductive feeds;
encapsulating with an encapsulant at least a portion of the semiconductor die and routing structure, a top portion of the routing structure exposed through a cavity formed in the encapsulant;
forming a conductive trace to interconnect the semiconductor die with the routing structure; and
attaching a component to the exposed top portion of the routing structure within the cavity.