US 12,243,841 B2
Electronic component embedded substrate and circuit module using the same
Toshiyuki Abe, Tokyo (JP); Yoshihiro Suzuki, Tokyo (JP); Hironori Chiba, Tokyo (JP); Tetsuya Yazaki, Tokyo (JP); and Hiroshige Ohkawa, Tokyo (JP)
Assigned to TDK Corporation, Tokyo (JP)
Appl. No. 17/618,666
Filed by TDK Corporation, Tokyo (JP)
PCT Filed Jun. 5, 2020, PCT No. PCT/JP2020/022236
§ 371(c)(1), (2) Date Dec. 13, 2021,
PCT Pub. No. WO2020/250815, PCT Pub. Date Dec. 17, 2020.
Claims priority of application No. 2019-110898 (JP), filed on Jun. 14, 2019.
Prior Publication US 2022/0238474 A1, Jul. 28, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 25/16 (2023.01); H01S 5/0233 (2021.01); H01S 5/024 (2006.01)
CPC H01L 24/24 (2013.01) [H01L 23/367 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/82 (2013.01); H01L 25/16 (2013.01); H01S 5/0233 (2021.01); H01S 5/02469 (2013.01); H01L 2224/19 (2013.01); H01L 2224/211 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24155 (2013.01); H01L 2224/24175 (2013.01); H01L 2224/244 (2013.01); H01L 2224/82106 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic component embedded substrate comprising:
a substrate including a plurality of wiring layers including at least first, second, and third wiring layers and a plurality of insulating layers including at least a first insulating layer positioned between the first and second wiring layers and a second insulating layer positioned between the first and third wiring layers, the plurality of wiring layers and the plurality of insulating layers being alternately stacked;
a first electronic component and a heat transfer block which are embedded in the first insulating layer;
a first wiring pattern positioned in the first wiring layer, the first wiring pattern including a first section facing one surface of the heat transfer block, a second section facing a main surface of the first electronic component, and a third section connecting the first and the second sections;
a second wiring pattern positioned in the second wiring layer and facing an other surface of the heat transfer block;
a third wiring pattern positioned in the third wiring layer and overlapping the first section of the first wiring pattern;
a first via conductor connecting the first section of the first wiring pattern and the one surface of the heat transfer block;
a second via conductor connecting the second wiring pattern and the other surface of the heat transfer block;
a third via conductor connecting the second section of the first wiring pattern and the electronic component; and
a fourth via conductor penetrating through the second insulating layer and connecting the third wiring pattern and the first section of the first wiring pattern,
wherein the third wiring pattern is exposed so as to define an electronic component mounting area for mounting a second electronic component, and
wherein the one surface and the other surface of the heat transfer block are insulated from each other, whereby the first and second wiring patterns are insulated from each other by the heat transfer block.