US 12,243,840 B2
Wirebondable interposer for flip chip packaged integrated circuit die
Edwin Loy, Fremont, CA (US); Yan Yang Zhao, Fremont, CA (US); and Chihhao Chen, Fremont, CA (US)
Assigned to SAMTEC, INC., New Albany, IN (US)
Filed by Samtec, Inc., New Albany, IN (US)
Filed on Jul. 24, 2020, as Appl. No. 16/937,922.
Claims priority of provisional application 62/878,466, filed on Jul. 25, 2019.
Prior Publication US 2021/0028140 A1, Jan. 28, 2021
Int. Cl. H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H04B 10/80 (2013.01); H04B 10/40 (2013.01)
CPC H01L 24/14 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/50 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/4985 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5387 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/05 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05076 (2013.01); H01L 2224/05078 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81815 (2013.01); H04B 10/40 (2013.01); H04B 10/808 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method of converting an IC die to a wirebondable electrical component, the method comprising the step of flip chip mounting the IC die to a first surface of at least one patterned electrically conductive layer of an interposer, wherein the interposer has wirebond pads at a second surface of the at least one patterned electrically conductive layer that is opposite the first surface along a transverse direction, the first surface abuts an electrically insulative surface of a first electrically insulative layer, and the second surface abuts an electrically insulative surface of a second electrically insulative layer that is spaced from the first electrically insulative layer along the transverse direction, and wherein the IC die has an active surface, and the active surface faces away from an external substrate when the wirebondable electrical component is wirebonded to the external substrate,
wherein the step of flip chip mounting comprises reflowing a plurality of solder bumps on the IC die to the first surface of the at least one patterned electrically conductive layer, and
wherein the first surface of the at least one patterned electrically conductive layer is exposed through first holes that extend through the first electrically insulative layer at a first side of the interposer, and the interposer has second holes in the second electrically insulative layer that expose the wirebond pads at the second surface of the at least one patterned electrically conductive layer, and
wherein the second electrically insulative layer extends continuously and uninterrupted along the second surface of the at least one patterned electrically conductive layer with the exception of the second holes.