US 12,243,828 B2
Microelectronic assemblies having topside power delivery structures
Bernd Waidhas, Pettendorf (DE); Carlton Hanna, Santa Jose, CA (US); Stephen Morein, San Jose, CA (US); Lizabeth Keser, San Diego, CA (US); and Georg Seidemann, Landshut (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/355,770.
Prior Publication US 2022/0415815 A1, Dec. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01); H01L 25/18 (2023.01); H05K 1/18 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 23/3675 (2013.01); H01L 23/481 (2013.01); H01L 24/24 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/0652 (2013.01); H01L 25/16 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H05K 1/181 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/24137 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19106 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic assembly, comprising:
a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source;
a mold material on the surface of the package substrate including a first microelectronic component, having a first surface and an opposing second surface, embedded in the mold material, a second microelectronic component embedded in the mold material, and a through-mold via (TMV), between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway;
a redistribution layer (RDL), having a first surface on the mold material and an opposing second surface, including a second conductive pathway electrically coupled to the TMV; and
a third microelectronic component at the second surface of the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the third microelectronic component, and the second surface of the first microelectronic component.