US 12,243,825 B2
Hybrid conductive vias for electronic substrates
Srinivas Pietambaram, Chandler, AZ (US); and Rahul Manepalli, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 21, 2021, as Appl. No. 17/326,569.
Prior Publication US 2022/0375866 A1, Nov. 24, 2022
Int. Cl. H01L 23/538 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 23/5381 (2013.01); H01L 23/5386 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a bridge die embedded in an embedding dielectric layer, the bridge die comprising a first surface and an opposing second surface;
a conductive via on and extending over the first surface of the bridge die, wherein the embedding dielectric layer is over the first surface of the bridge die and the conductive via is embedded in the embedding dielectric layer;
a fine pitch dielectric layer directly on the embedding dielectric layer, the fine pitch dielectric layer having an upper surface;
a coarse pitch dielectric layer on the upper surface of the fine pitch dielectric layer; and
at least one hybrid conductive via extending through the fine pitch dielectric layer and the coarse pitch dielectric layer to contact the conductive via, wherein the hybrid conductive via is on the upper surface of the fine pitch dielectric layer, and wherein the hybrid conductive via comprises a single conductive material.