US 12,243,823 B2
Semiconductor device having backside gate contact
Chun-Yuan Chen, Hsinchu (TW); Huan-Chieh Su, Hsinchu (TW); Cheng-Chi Chuang, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Sep. 16, 2021, as Appl. No. 17/476,962.
Claims priority of provisional application 63/181,719, filed on Apr. 29, 2021.
Prior Publication US 2022/0352074 A1, Nov. 3, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 23/535 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 21/0259 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 27/088 (2013.01); H01L 29/0665 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first gate all around transistor on a front side of a substrate, the first gate all around transistor including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the semiconductor nanostructure, and a gate electrode;
forming a second gate all around transistor of the semiconductor device, the second gate all around transistor disposed on the substrate at the front side of the semiconductor device, the second gate all around transistor including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the semiconductor nanostructure, and a gate electrode;
forming a shallow trench isolation region extending into the semiconductor device from a backside of the substrate that is opposite the front side; and
forming a backside gate plug extending into the substrate from the backside of the substrate and contacting the gate electrode of the first gate all around transistor, the backside gate plug laterally contacting the shallow trench isolation region at the backside of the substrate, wherein the forming the backside gate plug includes forming the backside gate plug in contact with the gate electrode of the second gate all around transistor.