US 12,243,822 B2
Method of manufacturing integrated circuit
Chih-Yu Lai, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Chih-Liang Chen, Hsinchu (TW); and Li-Chun Tien, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,572.
Application 18/447,572 is a division of application No. 17/459,756, filed on Aug. 27, 2021, granted, now 11,862,562.
Prior Publication US 2023/0387014 A1, Nov. 30, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 23/552 (2006.01); H01L 27/092 (2006.01); H01L 29/417 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 21/823871 (2013.01); H01L 23/5226 (2013.01); H01L 23/552 (2013.01); H01L 27/092 (2013.01); H01L 29/41725 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first transistor stack over a substrate, the first transistor stack comprising:
a first transistor of a first conductivity type; and
a second transistor of a second conductivity type different from the first conductivity type, the second transistor above the first transistor; and
forming a plurality of first conductive lines in a first metal layer above the first transistor stack, the plurality of first conductive lines comprising, over the first transistor stack:
a power conductive line configured to route power to the first transistor stack;
one or more signal conductive lines configured to route one or more signals to the first transistor stack; and
a shielding conductive line configured to shield the routed one or more signals on the one or more signal conductive lines, wherein the one or more signal conductive lines are between the power conductive line and the shielding conductive line.